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2. Pin Configurations and Pinouts
Table 2-1.
Pin Name
CS
SCK
SI
SO
WP
RESET
RDY/BUSY
Pin Configurations
Function
Chip Select
Serial Clock
Serial Input
Serial Output
Hardware Page Write Protect Pin
Chip Reset
Ready/Busy
Figure 2-1.
TSOP Top View, Type 1
Figure 2-2.
8-SOIC
RDY/BUSY
RESET
WP
NC
NC
VCC
1
2
3
4
5
6
28
27
26
25
24
23
NC
NC
NC
NC
NC
NC
SI
SCK
RESET
CS
1
2
3
4
8
7
6
5
SO
GND
VCC
WP
GND
NC
NC
NC
CS
SCK
SI
SO
7
8
9
10
11
12
13
14
22
21
20
19
18
17
16
15
NC
NC
NC
NC
NC
NC
NC
NC
Figure 2-3.
28-SOIC (1)
Figure 2-4.
CBGA Top View
through Package
GND
1
28
VCC
NC
NC
2
3
27
26
NC
NC
1
2
3
CS
4
25
WP
SCK
SI
5
6
24
23
RESET
RDY/BUSY
A
SO
7
22
NC
SCK
GND
VCC
NC
NC
NC
8
9
10
21
20
19
NC
NC
NC
B
C
CS RDY/BSY WP
NC
11
18
NC
SO
SI
RESET
NC
NC
NC
12
13
14
17
16
15
NC
NC
NC
Note:
1. This package is not recommended for new designs.
2
AT45DB021B
1937J–DFLSH–9/05
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